<p>This article introduces the knowledge about how to use the make command under linux. During the operation of the actual case, many people will encounter such a dilemma. Next, let the editor lead you to learn how to deal with these situations Bar! I hope you read it carefully and learn something!</p><p><br/></p><p><strong>How make Works</strong><br/>For those who don't know what's going on behind the scenes, the make command accepts targets like command line arguments. These targets are usually stored in a special file named makefile, and the file also contains the operations corresponding to the target. For more information, read our series on how makefiles work.</p><p>When the make command is executed for the first time, it scans the makefile for targets and their dependencies. If those dependencies are targets themselves, go ahead and scan the makefiles for those dependencies to build their dependencies, then compile them. Once the main dependencies are compiled, then build the main target (which is passed through the make command).</p><p>Now, suppose you have modified a certain source file, and you execute the make command again, it will only compile the target files related to the source file, so the final executable file saved after compiling plenty of time.</p><p><strong>make command example</strong><br/>The following is the test environment used in this article:</p><p>os —— ubunut 13.04
shell - bash 4.2.45
application —— gnu make 3.81</p><p>The following is the content of the project:</p><p>$ ls
anothertest.c makefile test.c test.h</p><p>The following is the content of the makefile:</p><p>all: test
test: test.o anothertest.o
gcc -wall test.o anothertest.o -o test
test.o: test.c
gcc -c -wall test.c
anothertest.o: anothertest.c
gcc -c -wall anothertest.c
clean:
rm -rf *.o test</p><p>Now let's look at some examples of make command applications under linux:</p><p><strong>1. A simple example</strong></p><p>In order to compile the whole project, you canSimply use make or pass the target all after the make command.</p><p>$ make
gcc -c -wall test.c
gcc -c -wall anothertest.c
gcc -wall test.o anothertest.o -o test</p><p>You can see the dependencies and actual targets created by the make command for the first time.</p><p>If you look at the contents of the directory again, there are some more .o files and executable files:</p><p>$ ls
anothertest.c anothertest.o makefile test test.c test.h test.o</p><p>Now, assuming you have made some changes to the test.c file, re-use make to compile the project:</p><p>$ make
gcc -c -wall test.c
gcc -wall test.o anothertest.o -o test</p><p>You can see that only test.o is recompiled, but the other test.o is not.</p><p>Now to clean all object files and executable test, you can use target clean:</p><p>$ make clean
rm -rf *.o test
$ ls
anothertest.c makefile test.c test.h</p><p>You can see that all .o files and the executable test are deleted.</p><p><strong>2. Make all targets always rebuild with the -b option</strong></p><p>So far, you may have noticed that the make command does not compile those since the above There are no changed files after the first compilation, but if you want to override make's default behavior, you can use the -b option.</p><p>Here is an example:</p><p>$ make
make: nothing to be done for `all'.
$ make -b
gcc -c -wall test.c
gcc -c -wall anothertest.c
gcc -wall test.o anothertest.o -o test</p><p>You can see that although the make command will not compile any files, make -b will force compilation of all object files and the final execution file.</p><p><strong>3. Use the -d option to print debug information</strong></p><p>If you want to know what actually did when make was executed, use the -d option.</p><p>Here is an example:</p><p>$ make -d | more
gnu make 3.81
copyright (c) 2006 free software foundation, inc.
this is free software; see the source for copying conditions.
there is no warranty; not even for merchantability or fitness for a
particular purpose.
this program built for x86_64-pc-linux-gnu
reading makefiles…
reading makefile `makefile'...
updating makefiles….
considering target file `makefile'.
looking for an implicit rule for `makefile'.
trying pattern rule with stem `makefile'.
trying implicit prerequisite `makefile.o'.
trying pattern rule with stem `makefile'.
trying implicit prerequisite `makefile.c'.
trying pattern rule with stem `makefile'.
trying implicit prerequisite `makefile.cc'.
trying pattern rule with stem `makefile'.
trying implicit prerequisite `makefile.c'.
trying pattern rule with stem `makefile'.
trying implicit prerequisite `makefile.cpp'.
trying pattern rule with stem `makefile'.
--more--</p><p>This is a long output, you also saw that I used the more command toDisplay the output page by page.</p><p><strong>4. Use the -c option to change the directory</strong></p><p>You can provide a different directory path to the make command, and the directory will be switched before looking for the makefile.</p><p>This is a directory, assuming you are in the current directory:</p><p>$ ls
file file2 frnd frnd1.cpp log1.txt log3.txt log5.txt
file1 file name with spaces frnd1 frnd.cpp log2.txt log4.txt</p><p>But the makefile of the make command you want to run is stored in the ../make-dir/ directory, you can do this:</p><p>$ make -c ../make-dir/
make: entering directory `/home/himanshu/practice/make-dir'
make: nothing to be done for `all'.
make: leaving directory `/home/himanshu/practice/make-dir</p><p>You can see that the make command first switches to a specific directory, executes there, and then switches back.</p><p><strong>5. Use the -f option to treat other files as makefiles</strong></p><p>If you want to rename the makefile, for example, name it my_makefile or something else Name, we want make to treat it as a makefile too, you can use the -f option.</p><p>make -f my_makefile</p><p>In this way, the make command will choose to scan my_makefile instead of makefile.</p><p><br/></p>
