How to use the compiling command of linux system?

The compiling command of linux system is Make. In linux system, make is a very important compiling command. Administrators use it to compile and install many open source tools through the command line, and programmers use it to manage their large and complex project compilation problems. Make is used to automate the task of compiling large-scale programs. It can automatically detect the parts of the program that need to be recompiled and issue corresponding compilation instructions.

Make Introduction Make is a utility program of linux system. It is used to manage the automatic compilation task of large-scale programs, automatically judge which part of the program needs to be recompiled, and send compilation instructions. Although, we are most common in the compilation of C language programs. However, make is not limited to a specific language, and it can be used in any language that can run the compiler through shell commands. In addition, you can even use make to describe any construction task, in which files need to be updated automatically after the files they depend on change.

The Make command of how Make works is just like a command line parameter to people who are not familiar with the mechanism behind it. Usually, these operations are stored in a special file called Makefile and correspond to the target. For more information, read a series of articles about how Makefiles works.

When the Make command is executed for the first time, it will scan the Makefile to find the target and the corresponding dependency. If these dependencies also need to be compiled into targets, you should continue to scan Makefile and establish their dependencies, and then compile. Once the main dependency is compiled, the main target will be compiled (this is entered through the make command).

Now, suppose you modify a source file, and you execute the make command again, it will only compile the target file related to the source file, so it saves a lot of time to compile the final executable file.

> Make command example the following is the test environment used in this paper:

OS —— Ubunut 13.04Shell —— Bash 4.2.45Application —— GNU Make 3.81

The following is the content of the project:

$ ls anotherTest.c Makefile test.c test.h

The following is the content of Makefile:

all: test test: test.o anotherTest.o gcc -Wall test.o anotherTest.o -o testtest.o: test.c gcc -c -Wall test.c anotherTest.o: anotherTest.c gcc -c -Wall anotherTest.c clean: rm -rf *.o test

Now let's look at some examples of the application of the make command under Linux:

1. A simple example In order to compile the whole project, you can simply use make or bring the target all after the make command.

$ make gcc -c -Wall test.c gcc -c -Wall anotherTest.c gcc -Wall test.o anotherTest.o -o test

You can see the dependencies created by the make command for the first time and the actual goal.

If you look at the contents of the directory again, there are some more. O files and executable files:

$ ls anotherTest.c anotherTest.o Makefile test test.c test.h test.o

Now, suppose you make some changes to the test.c file and reuse the make compilation project:

$ make gcc -c -Wall test.c gcc -Wall test.o anotherTest.o -o test

You can see that only Test.o has been recompiled, while the other test.o has not been recompiled.

Now clean up all the target files and executable files test, you can use the target clean:

$ make cleanrm -rf *.o test$ lsanotherTest.c Makefile test.c test.h

You can see that all the. o files and the execution file test have been deleted.

2. Let all targets always be re-established through the -B option. So far, you may notice that the make command will not compile files that have not changed since the last compilation. However, if you want to override the default behavior of make, you can use the -B option.

Here is an example:

$ makemake: Nothing to be done for `all’.$ make -Bgcc -c -Wall test.cgcc -c -Wall anotherTest.cgcc -Wall test.o anotherTest.o -o test

You can see that although the make command will not compile any files, make -B will force the compilation of all target files and final execution files.

3. Use the -d option to print debugging information. If you want to know what was actually done when make was executed, use the -d option.

This is an example:

$ make -d | moreGNU Make 3.81Copyright (C) 2006 Free Software Foundation, Inc.This is free software; see the source for copying conditions.There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR APARTICULAR PURPOSE.This program built for x86_64-pc-linux-gnuReading makefiles…Reading makefile ` Makefile’…Updating makefiles….Considering target file `Makefile’.Looking for an implicit rule for `Makefile’.Trying pattern rule with stem ` Makefile’.Trying implicit prerequisite `Makefile.o’.Trying pattern rule with stem `Makefile’.Trying implicit prerequisite ` Makefile.c’.Trying pattern rule with stem `Makefile’.Trying implicit prerequisite `Makefile.cc’.Trying pattern rule with stem ` Makefile’.Trying implicit prerequisite `Makefile.C’.Trying pattern rule with stem `Makefile’.Trying implicit prerequisite `Makefile.cpp’.Trying pattern rule with stem `Makefile’.--More--

This is a long output, and as you can see, I used the more command to display the output page by page.

4. Use the -C option to change the directory. You can provide different directory paths for the make command, and you will switch directories before looking for the Makefile.

This is a directory, assuming that you are in the current directory:

$ ls file file2 frnd frnd1.cpp log1.txt log3.txt log5.txtfile1 file name with spaces frnd1 frnd.cpp log2.txt log4.txt

But the Makefile of the make command you want to run is saved in the .. /make-dir/ directory. You can do this:

$ make -C ../make-dir/ make: Entering directory `/home/himanshu/practice/make-dir’ make: Nothing to be done for `all’. make: Leaving directory `/home/himanshu/practice/make-dir

You can see that the make command first cuts to a specific directory, executes there, and then switches back.

5. Use the -f option to treat other files as Makefiles. If you want to rename a Makefile, such as my_makefile or other names, we want Make to treat it as a makefile. You can use the -f option.

make -f my_makefile

In this way, the make command will choose to scan my_Makefile instead of makefile.